The present invention relates to power factor correction circuits, that is, circuits for reducing the distortion and harmonics generated in a power line feeding a power supply, and in particular a switched mode power supply. Power factor correction (PFC) circuits are utilized to reduce harmonics on power lines and in particular, make the circuit, including the attached load, appear to be a substantially purely resistive load. The aim of power factor correction circuits is to ensure that the AC voltage and current are substantially in phase. This improves efficiency and at the same time eliminates the generation of harmful harmonics.
In the past, passive solutions as shown in FIG. 1 have been employed. An inductor is provided at the output of the rectifier. Because the inductor operates at the line frequency, the physical size and inductance size are normally very large, requiring high costs and increasing size of the circuit. The input current waveform is smoothed, but typically does not meet today's regulation requirements.
FIG. 2 shows another prior art approach that provides an active solution wherein a controllable switch S is added together with a series inductor ahead of the rectifier. This switch is turned on for a short time period every half cycle of the line frequency, for example, 120 Hz or 100 Hz. Manufacturers use this method to smooth the input current which may satisfy some applicable regulation standards, in particular in Japan, but may not meet the strict IEC standard for the European markets. Also the inductor operates at the line frequency and its physical size and inductance are still large, resulting in still high costs and circuit size.
A third approach is another active solution which uses high frequency full boost power factor correction. This is the most popular PFC control method and is shown in FIG. 3 providing DC voltage to a motor drive inverter INV driving a motor ML. A switch, for example an IGBT Q1, is switched at high switching frequency normally in the 50 KHz to 100 KHz range. It can achieve nearly 100% power factor which actually exceeds most regulation standards. Because of the high frequency PWM, it requires a small physical size inductor and a small size inductance. However, even this circuit has drawbacks. In particular, the high frequency PWM switching causes high switching losses, less efficiency and creates electromagnetic interference (EMI) noise and 100% PFC may be more than is necessary for many design applications.
An aim of the present invention is to meet applicable regulation standards but not necessarily exceed such standards thereby to trade off power factor for reduced losses and increased efficiency by reducing switching losses and noise generation. FIG. 4 shows waveforms of the conventional active high frequency full boost PFC circuit shown in FIG. 3.
Another aim of the present invention is to provide a circuit and method of blanking or disabling a pulse width modulation signal used in a power factor correction circuit, thereby reducing switching losses while otherwise providing for an efficient circuit.
An additional aim of the present invention is to provide a circuit and method for controlling DC bus voltage in a power factor correction circuit to provide a preferred current waveform.